NMOS器件ESD特性模拟

NMOS管I-V曲线在ESD(electrostatic discharges)脉冲电流作用下呈现出反转特性,其维持电压VH、维持电流IH、触发电压VB、触发电流IB以及二次击穿电流等参数将会影响NMOS管器件的抗ESD能力。文章通过采用SILVACO软件,对1.0μm工艺不同沟长和工艺条件的NMOS管静电放电时的峰值电场、晶格温度以及VH进行了模拟和分析。模拟发现,在ESD触发时,增加ESD注入工艺将使结峰值场强增强,VH减小、VB减小,晶格温度降低;器件沟长和触发电压VB具有明显正相关特性,但对VH基本无影响。最后分析认为NMOS管ESD失效主要表现为高电流引起的热失效,而电场击穿引起的介质失效是次要的。

Simulation of NMOS Transistor ESD Characteristics

Snapback characteristics have been observed on the NMOS transistor I-V curves when an ESD (electrostatic discharge)pulse current is triggered. The NMOS transistor ESD characteristics would be affected by such parameters as the hold voltage VH, hold current IH, trigger voltage VB, trigger current IB and secondary breakdown current. By using the SILVACO process and device simulator, the peak electric field, lattice temperature profile and VH during electrostatic discharges have been simulated and analyzed for NMOS transistors with different channel lengths and fabricated under different process conditions for 1.0 μ m process technology. It is found through the simulation that an additional ESD implantation step in the process flow would increase the peak electric field when ESD discharge is triggered, but the VH, VB and lattice temperature would be decreased. The transistor channel length is obviously positively correlated to the trigger voltage VB, but it has little effect on VH. It is concluded that ESD failures of NMOS transistors are mainly caused by the thermal failures induced by high current density, and the dielectric failures induced by electric field breakdown only have a minor effect on ESD failures.