高性能众核处理器芯片时钟网络设计

随着芯片工艺演进与设计规模增加，高性能众核处理器芯片时钟网络设计面临时序和功耗的全方位挑战。为降低芯片时钟网络功耗并缓解时钟网络分布受片上偏差影响导致的时钟偏斜，在H-Tree+MESH混合时钟网络结构的基础上，结合新一代众核处理器芯片面积大及核心时钟网络分布广的特点，基于标准多源时钟树设计策略构建多源时钟树综合（MRCTS）结构，通过全局H-Tree时钟树保证芯片不同区域间时钟偏斜的稳定可控，利用局部时钟树综合进行关键路径的时序优化以实现时序收敛。实验结果表明，MRCTS能在保证时钟延时、时钟偏斜等性能参数可控的基础上，有效降低时钟网络的负载和功耗，大幅压缩综合子模块的布线资源，加速关键路径的时序收敛，并且在相同电源电压和时钟频率的实测条件下，可获得约22.15%的时钟网络功耗优化。

Chip Clock Network Design for High-Performance Many-Core Processor

With the evolution of chip technology and an increase in the design scale, the chip clock network design of high-performance many-core processor is facing many challenges, including the power consumption and timing.In order to reduce the power consumption of the chip clock network and the clock skew caused by the On-Chip Variation(OCV) of clock network distribution, this study builds a Multi-Root Clock Tree Synthesis(MRCTS) structure by using the standard multi-source clock tree design strategy.The construction of MRCTS is based on the H-Tree+MESH hybrid clock network structure, and takes into account the large chip area of the new generation many-core processors and the wide distribution of core clock networks.MRCTS ensures stable and controllable clock skew between different regions of the chip through the global H-Tree clock tree and uses local Clock Tree Synthesis(CTS) to optimize the timing of the critical paths and achieve a timing convergence.The experimental results show that MRCTS can effectively reduce the load and power consumption of the clock network by ensuring the controllability of the clock delay, clock skew, and other performance parameters.In addition, it greatly compress the routing resources of each integrated sub-module and accelerates the timing closure of critical paths.Particularly under the measured conditions of the same supply voltage and clock frequency, MRCTS can optimize the clock network power consumption by approximately 22.15%.