低功耗异构计算架构的高光谱遥感图像分类研究

高光谱图像分类算法通常需要逐点对图像中的像素点进行迭代处理，计算复杂度及并行程度存在较大差异。随着高光谱遥感图像空间、光谱和辐射分辨率的不断提升，这些算法无法满足实时处理海量遥感图像数据的需求。通过分析NPU存储计算一体化模式与遥感图像分类算法的实现步骤，设计低功耗CPU+NPU异构资源计算架构的低秩稀疏子空间聚类（LRSSC）算法，将数据密集型计算转移至NPU，并利用NPU数据驱动并行计算和内置AI加速，对基于机器学习算法的海量遥感数据进行实时分类。受到big.LITTLE计算范式的启发，CPU+NPU异构资源计算架构由8 bit和低精度位宽NPU共同组成以提高整体吞吐量，同时减少图网络推理过程中的能量损耗。实验结果表明，与CPU计算架构和CPU+GPU异构计算架构的LRSSC算法相比，CPU+NPU异构计算架构的LRSSC算法在Pavia University遥感数据集下的计算速度提升了3~14倍。

Research on Hyperspectral Remote Sensing Image Classification Using Low-Power Heterogeneous Computing Architecture

Hyperspectral image classification algorithms typically need to iteratively process the pixels in the image point by point, which significantly differ in computational complexity and parallelism.However, with the significant improvement of the spatial, spectral, and radiometric resolution for Hyperspectral Remote Sensing(HRS) images, these algorithms cannot fulfill the requirements to timely handle massive datasets.Therefore, a Low-Rank Sparse Subspace Clustering(LRSSC) algorithm based on heterogeneous Central Processing Unit(CPU)+Neural-network Processing Unit(NPU) computing architecture is designed by optimizing the NPU storage and computing integration mode and the implementation steps of the classification algorithm, thus offloading data-intensive computations to the NPU.This study uses NPU data-driven parallel computing with internal Artificial Intelligence(AI) acceleration to support real-time classification of massive hyperspectral data based on machine learning algorithms.Inspired by big.LITTLE computing paradigm, the proposed CPU+NPU computing architecture consists of 8 bit and low-precision bit-width NPUs to improve the overall throughput while reducing energy consumption during graph network inference.The simulations with Pavia University hyperspectral dataset show that compared with the LRSSC algorithms using the CPU computing architecture and heterogeneous CPU+Graphics Processing Unit(GPU) computing architecture, the computational speed of the designed LRSSC algorithm using the heterogeneous CPU+NPU computing architecture is significantly reduced by 3-14 times.