Interlayer cooling potential in vertically integrated packages |
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Authors: | T. Brunschwiler B. Michel H. Rothuizen U. Kloter B. Wunderle H. Oppermann H. Reichl |
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Affiliation: | 1. Zurich Research Laboratory, IBM Research GmbH, 8803, Rüschlikon, Switzerland 2. Fraunhofer Institute for Reliability and Microintegration, 13355, Berlin, Germany 3. Electrical Engineering, Technische Universit?t Berlin, 13355, Berlin, Germany
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Abstract: | The heat-removal capability of area-interconnect-compatible interlayer cooling in vertically integrated, high-performance chip stacks was characterized with de-ionized water as coolant. Correlation-based predictions and computational fluid dynamic modeling of cross-flow heat-removal structures show that the coolant temperature increase due to sensible heat absorption limits the cooling performance at hydraulic diameters ≤200 μm. An experimental investigation with uniform and double-side heat flux at Reynolds numbers ≤1,000 and heat transfer areas of 1 cm2 was carried out to identify the most efficient interlayer heat-removal structure. The following structures were tested: parallel plate, microchannel, pin fin, and their combinations with pins using in-line and staggered configurations with round and drop-like shapes at pitches ranging from 50 to 200 μm and fluid structure heights of 100–200 μm. A hydrodynamic flow regime transition responsible for a local junction temperature minimum was observed for pin fin in-line structures. The experimental data was extrapolated to predict maximal heat flux in chip stacks having a 4-cm2 heat transfer area. The performance of interlayer cooling strongly depends on this parameter, and drops from >200 W/cm2 at 1 cm2 and >50 μm interconnect pitch to <100 W/cm2 at 4 cm2. From experimental data, friction factor and Nusselt number correlations were derived for pin fin in-line and staggered structures. |
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