基于冗余子级的流水线ADC校准技术

提出了基于冗余子级的流水线ADC后端校准技术,采用精度较高的流水线冗余子级代替参考ADC,对流水线ADC的各个子级校准,替代了对整个ADC的校准,使校准系统无需降频同步,较好地解决了传统校准系统中主信号通路与参考ADC信号通路不同步的问题。对Matlab/Simulink中搭建的精度为16位、采样频率为10 MS/s的流水线ADC进行仿真,结果表明,当输入信号频率为4.760 5 MHz时,经过校准,流水线ADC的有效位和无杂散动态范围分别由9.37位和59.96 dB提高到15.32位和99.55 dB。进一步的FPGA硬件验证结果表明,流水线ADC的有效位和无杂散动态范围分别为12.73位和98.62 dB,初步验证了该校准算法的可行性。

A Calibration Technique for Pipeline ADC Based on Redundant Stage

A digital background calibration technique for pipeline analog-to-digital converter (ADC) based on redundant sub-stage was proposed. A more accurate redundant sub-stage was used to replace the reference ADC, and a method of calibrating each sub-stage was used to replace the method of calibrating the whole ADC. In this way, the down sampling and synchronization modules were not required in the calibration system, and thus the problem of non-synchronization could be solved which occurred between the main ADC signal path and reference ADC signal path in the traditional ADC calibration system. The entire proposed calibration system was modeled in Matlab/Simulink. The simulation results showed that the ENOB and SFDR of the 16-bit pipelined ADC with sampling rate of 10 MS/s were improved from 9.37-bit to 15.32-bit and 59.96 dB to 99.55 dB respectively after calibration. FPGA verification was implemented, and Spectra analysis showed that the ENOB and SFDR of 16-bit pipelined ADC were 12.73-bit and 98.62 dB respectively after calibration.