一种12位100 MS/s流水线ADC的设计

设计了一种12位100 MS/s流水线型模数转换器。采用3.5位/级的无采保前端和运放共享技术以降低功耗；采用首级多位数的结构以降低后级电路的输入参考噪声。采用一种改进型的双输入带电流开关的运放结构,以解决传统运放共享结构所引起的记忆效应和级间串扰问题。在TSMC 90 nm工艺下,采用Cadence Spectre进行仿真验证,当采样时钟频率为100 MS/s,输入信号频率为9.277 34 MHz时,信干噪比(SNDR)为71.58 dB,无杂散动态范围(SFDR)为86.32 dB,电路整体功耗为220.8 mW。

Design of a 12-Bit 100 MS/s Pipelined ADC in 90 nm CMOS Process

A 12-bit 100 MS/s pipelined ADC (analog-to-digital converter) was designed. This converter adopted a 3.5 bit first stage without SHA. The rest used opamp-sharing technology to reduce power consumption. The input-referred noise from post stages could be reduced by using multi-bit first stage. Conventional opamp-sharing structure would lead to memory effect and crosstalk between the two successive opamp-sharing stages. An improved opamp with dual input differential pair and current switch was employed to tackle this problem. The simulation results showed that the signal to noise and distortion ratio (SNDR) and the spurious free dynamic range (SFDR) of the converter were 71.58 dB and 86.32 dB respectively when an input signal of 9.277 34 MHz was imported to the converter under 100 MS/s sample rate. The whole power dissipation of the converter was 220.8 mW.