| 一种新型低漏电ESD电源箝位电路 |
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| 引用本文： | 李晓云,陈后鹏,李喜,王倩,张琪,范茜,雷宇,宋志棠. 一种新型低漏电ESD电源箝位电路[J]. 微电子学, 2016, 46(4): 572-575 |
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| 作者姓名： | 李晓云 陈后鹏 李喜 王倩 张琪 范茜 雷宇 宋志棠 |
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| 作者单位： | 中国科学院上海微系统与信息技术研究所 信息功能材料国家重点实验室, 上海200050,中国科学院上海微系统与信息技术研究所 信息功能材料国家重点实验室, 上海200050,中国科学院上海微系统与信息技术研究所 信息功能材料国家重点实验室, 上海200050,中国科学院上海微系统与信息技术研究所 信息功能材料国家重点实验室, 上海200050,中国科学院上海微系统与信息技术研究所 信息功能材料国家重点实验室, 上海200050,中国科学院上海微系统与信息技术研究所 信息功能材料国家重点实验室, 上海200050,中国科学院上海微系统与信息技术研究所 信息功能材料国家重点实验室, 上海200050,中国科学院上海微系统与信息技术研究所 信息功能材料国家重点实验室, 上海200050 |
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| 基金项目： | 国家集成电路重大专项(2009ZX02023-003)；国家自然科学基金资助项目(61176122)；中国科学院战略性先导科技专项(XDA09020402)；国家重点基础研究发展计划资助项目(2013CBA01900) |
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| 摘 要： | 在到达纳米级工艺后,传统的静电放电防护(ESD)电源箝位电路的漏电对集成电路芯片的影响越来越严重。为降低漏电,设计了一种新型低漏电ESD电源箝位电路,该箝位电路通过2个最小尺寸的MOS管形成反馈来降低MOS电容两端的电压差。采用中芯国际40 nm CMOS工艺模型进行仿真,结果表明,在相同的条件下,该箝位电路的泄漏电流仅为32.59 nA,比传统箝位电路降低了2个数量级。在ESD脉冲下,该新型ESD箝位电路等效于传统电路,ESD器件有效开启。
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| 关 键 词： | 静电放电防护 电源箝位电路 低漏电 |
A Novel Low-Leakage ESD Power-Rail Clamp Circuit |
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| LI Xiaoyun,CHEN Houpeng,LI Xi,WANG Qian,ZHANG Qi,FAN Xi,LEI Yu and SONG Zhitang. A Novel Low-Leakage ESD Power-Rail Clamp Circuit[J]. Microelectronics, 2016, 46(4): 572-575 |
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| Authors: | LI Xiaoyun CHEN Houpeng LI Xi WANG Qian ZHANG Qi FAN Xi LEI Yu SONG Zhitang |
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| Affiliation: | State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Micro-System and Information Technology, Chinese Academy of Sciences, Shanghai 200050, P. R. China,State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Micro-System and Information Technology, Chinese Academy of Sciences, Shanghai 200050, P. R. China,State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Micro-System and Information Technology, Chinese Academy of Sciences, Shanghai 200050, P. R. China,State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Micro-System and Information Technology, Chinese Academy of Sciences, Shanghai 200050, P. R. China,State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Micro-System and Information Technology, Chinese Academy of Sciences, Shanghai 200050, P. R. China,State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Micro-System and Information Technology, Chinese Academy of Sciences, Shanghai 200050, P. R. China,State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Micro-System and Information Technology, Chinese Academy of Sciences, Shanghai 200050, P. R. China and State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Micro-System and Information Technology, Chinese Academy of Sciences, Shanghai 200050, P. R. China |
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| Abstract: | The leakage current of the conventional electrostatic discharge (ESD) power-rail clamp circuit is making an increasingly serious impact on integrated circuit (IC) chips when the nano-scale process is coming. To reduce the leakage current, a novel ESD power-rail clamp circuit was proposed. A feedback circuit, which was composed of two minimum dimension MOS transistors, was designed to lower the voltage drop on the two ends of the MOS capacitor. Based on SMIC 40 nm CMOS technology, Spectre simulation results showed that the leakage current of this novel circuit was only 32.59 nA. Compared with the conventional circuit, the present leakage current had been reduced by over two orders of magnitude. Under ESD condition, the ESD device of the proposed circuit was equivalent to the conventional circuit, and could be triggered on to discharge current. |
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