Scheduling and Partitioning Schemes for Low Power Designs Using Multiple Supply Voltages |
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Authors: | Ling Wang Yingtao Jiang Henry Selvaraj |
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Affiliation: | (1) Department of Computer Science and Technology, Harbin Institute of Technology, Harbin, 150001, P. R. China;(2) Department of Electrical & Computer Engineering, University of Nevada, Las Vegas, Las Vegas, NV 89154, USA |
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Abstract: | This paper presents a time-constrained algorithm and a resource-constrained algorithm to minimize the power consumption with
resources operating at multiple voltages. The input to both schemes is an unscheduled data flow graph (DFG), and the timing
or the resource constraints. In the paper, partitioning is considered with scheduling in the proposed algorithms as multiple
voltage design can lead to an increase in interconnection complexity at layout level. That is, in the proposed algorithms
power consumption is first reduced by the scheduling step, and then the partitioning step takes over to decrease the interconnection
complexity. Both time-constrained and resource-constrained algorithms have time complexity of o(n2), where n is the number of nodes in the DFG. Experiments with a number of DSP benchmarks show that the proposed algorithms achieve
the power reduction under timing constraints and resource constraints by an average of 46.5 and 20%, respectively. |
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Keywords: | low power multiple supply voltages partitioning resource constraints timing constraints scheduling |
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