A CMOS DCO design using delay programmable differential latches and a novel digital control scheme

A novel 16-bit CMOS digitally controlled oscillator (DCO) is described. This CMOS DCO design is based on a delay programmable differential latch and a novel digital control scheme which yields improved phase noise characteristics. Simulations of a 4-stage CMOS DCO using the 0.5 μm Agilent CMOS process parameters achieved a controllable frequency range of 750 MHz–1.6 GHz with a monotone tuning range of around 1 GHz. Monte Carlo simulations indicate that the time-period jitter due to random supply voltage fluctuations is under 250 ps for worst-case considerations. Also, phase noise was found to be in the range of −175 dBc at a frequency of 600 KHz from the carrier at 1.5 GHz (for digital control word of 1512 H) after numerous iterations of Monte Carlo simulations. FFT analysis indicate a total harmonic distortion (THD) of around − 57 dB for the DCO output signal. This CMOS design would thus provide considerable performance enhancement in digital PLL applications.