| 一种3.3 V 9位50 MS/s CMOS流水线A/D转换器 |
| |
| 引用本文： | 王韧,刘敬波,秦玲,陈勇,赵建民.一种3.3 V 9位50 MS/s CMOS流水线A/D转换器[J].微电子学,2006,36(5):651-654,658. |
| |
| 作者姓名： | 王韧 刘敬波 秦玲 陈勇 赵建民 |
| |
| 作者单位： | 1. 电子科技大学,微电子与固体电子学院,四川,成都,610054
2. 深圳艾科创新微电子有限公司,广东,深圳,518057 |
| |
| 摘 要： | 设计了一种3.3 V 9位50 MS/s CMOS流水线A/D转换器。该A/D转换器电路采用1.5位/级,8级流水线结构。相邻级交替工作,各级产生的数据汇总至数字纠错电路,经数字纠错电路输出9位数字值。仿真结果表明,A/D转换器的输出有效位数(ENOB)为8.712位,信噪比(SNR)为54.624 dB,INL小于1 LSB,DNL小于0.6 LSB,芯片面积0.37 mm2,功耗仅为82 mW。
|
| 关 键 词： | A/D转换器 流水线结构 放大器 比较器 |
| 文章编号： | 1004-3365（2006）05-0651-04 |
| 收稿时间： | 2006-01-10 |
| 修稿时间： | 2006-01-102006-04-28 |
A 3.3 V 9-Bit 50 MS/s CMOS Pipeline Analog-to-Digital Converter |
| |
| WANG Ren,LIU Jing-bo,QIN Ling,CHEN Yong,ZHAO Jian-min.A 3.3 V 9-Bit 50 MS/s CMOS Pipeline Analog-to-Digital Converter[J].Microelectronics,2006,36(5):651-654,658. |
| |
| Authors: | WANG Ren LIU Jing-bo QIN Ling CHEN Yong ZHAO Jian-min |
| |
| Affiliation: | 1. Univ. of Elec. Sci. and Technol . of China, School of Microelectronics and Solid-State Electronics, Chengdu, Sichuan 610054, P. R. China 2. Ark Microelectronics(Shenzhen |
| |
| Abstract: | A 3.3 V,9-bit,50 MS/s pipeline analog-to-digital converter(ADC) is presented,in which an 8-stage(1.5-bit /stage) pipelining architecture is adopted.Each stage resolved two bits and the resulting 16 bits are combined with digital correction to yield 9 bits at the output of the ADC.Simulation results show that the ADC achieved a signal-to-noise ratio of 54.624 dB,maximum differential nonlinearity of 0.6 LSB,maximum integral nonlinearity of 1 LSB,and an ENOB of 8.712 bits with only 82 mW of power. |
| |
| Keywords: | Analog-to-digital converter Pipelining architecture Amplifier Comparator |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ |
|
