Design automation to suppress cable discharge event (CDE) induced latchup in 90 nm CMOS ASICs |
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Authors: | Ciaran J. Brennan Kiran Chatty Jeff Sloan Paul Dunn Mujahid Muhammad Robert Gauthier |
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Affiliation: | aIBM Microelectronics, 1000 River Road, MS863M, Essex Junction, VT 05452, USA |
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Abstract: | Design automation tools have been developed to suppress CDE-induced latchup in CMOS ASICs. The tools govern the placement of I/Os and cores subject to CDE and automate the insertion of well and substrate contacts with varying periodicities around CDE susceptible cells according to rules derived from an analytical latchup model. |
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