A 6.25 Gb/s equalizer in 0.18μm CMOS technology for high-speed SerDes |
| |
引用本文: | 张明科,胡庆生.A 6.25 Gb/s equalizer in 0.18μm CMOS technology for high-speed SerDes[J].半导体学报,2013(12):115-121. |
| |
作者姓名: | 张明科 胡庆生 |
| |
摘 要: | This paper presents a 0.18μm CMOS 6.25 Gb/s equalizer for high speed backplane communication. The proposed equalizer is a combined one consisting of a one-tap feed-forward equalizer (FFE) and a two-tap half-rate decision feedback equalizer (DFE) in order to cancel both pre-cursor and post-cursor ISI. By employing an active-inductive peaking circuit for the delay line, the bandwidth of the FFE is increased and the area cost is minimized. CML-based circuits such as DFFs, summers and multiplexes all help to improve the speed of DFEs. Measurement results illustrate that the equalizer operates well when equalizing 6.25 Gb/s data is passed over a 30-inch channel with a loss of 22 dB and consumes 55.8 mW with the supply voltage of 1.8 V. The overall chip area including pads is 0.3 × 0.5 mm^2.
|
关 键 词: | 判决反馈均衡器 CMOS技术 SerDes Gb 慢性粒细胞白血病 芯片面积 成本最小化 高速背板 |
本文献已被 维普 等数据库收录! |
| 点击此处可从《半导体学报》浏览原始摘要信息 |
|
点击此处可从《半导体学报》下载全文 |
|