基于FPGA的可配置时序信号发生系统设计

为了满足测试环节对特殊时序信号的要求，设计了一种可配置时序信号发生系统，可实现多路时序信号的输出。该时序信号发生系统由上位机和下位机两部分组成，上位机软件对输出的时序信号进行配置，下位机采用STM32+FPGA相结合的硬件结构，实现配置后的多路时序信号输出。由于下位机的STM32芯片与FPGA采用两个不同的时钟，因此在FPGA内使用异步FIFO实现与STM32芯片的数据通信，有效实现了两者之间的并行数据传输。

Design of configurable timing signal generator based on FPGA

In order to meet the requirements of the special timing signal in the test section, a configurable timing signal generation system is designed to realize the output of the multi channel timing signal. The signal generating system consists of two parts: the host computer and the slave computer. The host computer software is used to configure the output timing, and the slave computer using hardware structure through combination of STM32+FPGA. As the STM32 chip of the slave computer and FPGA using two different clocks, so the design uses asynchronous FIFO in the FPGA chip to achieve data communication to STM32, which can achieve effectively the parallel data transmission between the two.