Enhancement of test data compression with multistage encoding |
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Authors: | S Sivanantham M Padmavathy Ganga Gopakumar PS Mallick J Raja Paul Perinbam |
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Affiliation: | 1. School of Electrical Engineering, VIT University, Vellore 632014, Tamil Nadu, India;2. School of Electronics Engineering, VIT University, Vellore 632014, Tamil Nadu, India;3. Sankalp and KPIT Semiconductors Pvt. Ltd, Bangalore, Karnataka, India;4. Department of ECE, KCG College of Technology, Chennai 600097, Tamil Nadu, India |
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Abstract: | In this paper, we present two multistage compression techniques to reduce the test data volume in scan test applications. We have proposed two encoding schemes namely alternating frequency-directed equal-run-length (AFDER) coding and run-length based Huffman coding (RLHC). These encoding schemes together with the nine-coded compression technique enhance the test data compression ratio. In the first stage, the pre-generated test cubes with unspecified bits are encoded using the nine-coded compression scheme. Later, the proposed encoding schemes exploit the properties of compressed data to enhance the test data compression. This multistage compression is effective especially when the percentage of do not cares in a test set is very high. We also present the simple decoder architecture to decode the original data. The experimental results obtained from ISCAS'89 benchmark circuits confirm the average compression ratio of 74.2% and 77.5% with the proposed 9C-AFDER and 9C-RLHC schemes respectively. |
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Keywords: | VLSI testing Test data compression Huffman coding FDR coding Design for testability Low-power testing |
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