On the development of high-throughput and area-efficient multi-mode cryptographic hash designs in FPGAs |
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Authors: | H.E. Michail G.S. Athanasiou G. Theodoridis C.E. Goutis |
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Affiliation: | 1. Electrical Engineering, Computer Engineering and Informatics Department, Cyprus University of Technology, 3036 Lemesos, Cyprus;2. Antcor – Advanced Network Technologies S.A., Sorou Str. 12, 15125 Marousi, Greece;3. VLSI Design Laboratory, Electrical and Computer Engineering Department, University of Patras, 26500 Patras, Greece |
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Abstract: | In this paper, area-efficient and high-throughput multi-mode architectures for the SHA-1 and SHA-2 hash families are proposed and implemented in several FPGA technologies. Additionally a systematic flow for designing multi-mode architectures (implementing more than one function) of these families is introduced. Compared to the corresponding architectures that are produced by a commercial synthesis tool, the proposed ones are better in terms of both area (at least 40%) and throughput/area (from 32% up to 175%). Finally, the proposed architectures outperform similar existing ones in terms of throughput and throughput/area, from 4.2× up to 279.4× and from 1.2× up to 5.5×, respectively. |
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Keywords: | Hash Authentication Multi-mode FPGA |
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