Chip area estimation method for VLSI chip floor plan |
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| Authors: | Kitazawa H Ueda K |
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| Affiliation: | NTT Atsugi Electrical Communication Laboratory, Atsugi, Japan; |
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| Abstract: | A chip area estimation method is presented, which consists of intrablock area calculation based on empirically obtained block data and interblock channel area calculation. The method is used in a chip floor program for hierarchical standard-cell VLSI layout design. By applying to several practical circuits, it is shown that the estimation error is within ±10%. |
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