深亚微米CMOS集成电路抗热载流子效应设计

热载流子效应(HCE)、电介质击穿、静电放电，以及电迁移等失效机理，已经对VLSI电路的长期可靠性造成了极大的威胁。其中，热载流子效应是最主要的失效机理之一。影响CMOS电路热载流子效应的因素有：晶体管的几何尺寸、开关频率、负载电容、输入速率以及晶体管在电路中的位置。通过对这些因素的研完，提出了CMOS电路热载流子可靠性设计的通用准则。

Considerations on Hot-Carrier Effects in the Design of Deep Submicron CMOS IC's

Failure mechanisms, such as hot-carrier effect (HCE), dielectric breakdown, electro-static discharge (ESD) and electromigration, pose serious threat to the long-term reliability of VLSI circuits. And HCE is one of the most common failure mechanisms. Factors leading to hot-carrier effects in CMOS IC's include transistor size, switching frequency, load capacitance, input rate and the location of transistors in the IC. These factors are investigated and a number of general rules for design are presented based on the investigation, to ensure hot-carrier reliability.