| LDPC码译码器的设计与实现 |
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| 引用本文： | 朱联祥,何凯.LDPC码译码器的设计与实现[J].电视技术,2013,37(7). |
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| 作者姓名： | 朱联祥 何凯 |
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| 作者单位： | 重庆邮电大学信号与信息处理重庆市重点实验室,重庆,400065 |
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| 摘 要： | 由于传统的LLR BP译码算法不易于FPGA实现,为了降低实现复杂度,采用一种改进的LLR BP译码实现方法,设计了一种码长为40、码率为0.5的规则LDPC码译码器,并完成了FPGA仿真实现.仿真和综合的结果表明,所设计的译码器吞吐量达到15.68 Mbit/s,且译码器的资源消耗适中.
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| 关 键 词： | LDPC码 LLRBP 译码器 FPGA |
| 收稿时间： | 8/7/2012 12:00:00 AM |
| 修稿时间： | 2012/9/24 0:00:00 |
Design and Implementation of LDPC code decoder |
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| Zhu Lian-xiang and He Kai.Design and Implementation of LDPC code decoder[J].Tv Engineering,2013,37(7). |
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| Authors: | Zhu Lian-xiang and He Kai |
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| Affiliation: | Chongqing University of Posts and Telecommunications,Chongqing University of Posts and Telecommunications |
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| Abstract: | As a result of the traditional LLR BP decoding algorithm is not easy to be implemented with FPGA, in order to reduce the complexity of implementation, this paper adopts a modified LLR BP decoding implementation method, design a kind of LDPC code decoder and implemented in FPGA for the regular LDPC code,whose code length is 40 and code rate is 0.5.The simulation and synthesis results show, the decoder throughput reached 15.68Mbps,and the resource consumption of decoder is moderate. |
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| Keywords: | Low Density Parity Check(LDPC) codes LLR BP decoder FPGA |
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