异步集成电路标准单元的设计与实现

设计异步集成电路时，常用的异步标准单元的分类、电路设计方法和电路结构．详细介绍了C单元和异步数据通路的设计与实现，提出了一种异步实现结构的异步加法单元、异步比较单元和异步选择单元电路．利用设计的异步标准单元构成了一个适用于Viterbi解码器的异步ACS(加法器一比较器一选择器)，并通过0．6μmCMOS工艺进行投片验证．当芯片工作电压为5V，工作频率为20MHz时的功耗为75．5mW．芯片的平均响应时问为19．18DS，仅为最差响应时间23．37ns的82％．从而验证了异步标准单元的正确性和异步电路在性能方面较同步电路存在的优势．

Design and Implementation of Asynchronous Integrate Circuits Standard Cells

The categor ies, circuits design method and architectur es for asynchronous standard cells are described.The design and implementation of C element and asynchronous data- path are int roduced. T he circuits of asynchronous adder unit, asynchronous comparator unit , and asynchronous selector unit are proposed.U sing these standar d cells, an asynchro nous ACS ( A dd-Compare-Select) processor for Viterbi decoderis formed. It has been fabr icated in 0. 6 Lm CMOS process. At a supply vo ltag e o f 5 V, w hen it operatesat 20 MHz, the pow er consumpt ion is 75. 5 mW. The result s of per formance test of asynchronous 4bit ACS pro cessor show that the averag e case r espo nse time 19. 18 ns is only 82% the w or st-case responsetime 23. 37 ns. T he cor rectness o f asynchro nous standard cells has been proved. It reveals that the asynchronouscircuit s have some performance advantages than the sy nchr ono us ones.