Managing data caches using selective cache line replacement

As processor performance continues to improve, more demands are being placed on the performance of the memory system. The caches employed in current processor designs are very similar to those described in early cache studies. In this paper, a detailed characterization of data cache behavior for individual load instructions is given. It will be shown that by selectively allocating cache lines according the characteristics of individual load instructions, overall performance can be improved for both the data cache and the memory system. This approach can improve some aspects of memory performance by as much as 60 percent on existing executables. This work was supported by National Science Foundation Grants CCR-94-03651, CCR-92-13651, CCR-92-13627, MIP-92-57259, and generous grants from the SUN Microsystems and Tektronix corporations.