基于分段预留法的互连线二维电容提取技术

随着制造工艺的不断演进、电路规模的不断增大,集成电路逐渐进入后摩尔时代。如何准确快速地进行寄生电容参数提取,对于保证设计质量、减少成本和缩短设计周期变得越来越重要。文章提出了一种基于分段预留法的二维电容提取技术,该技术基于改进的有限差分法,采用非均匀网格划分和求解不对称系数矩阵方程,模拟互连结构横截面,可以高效计算出主导体的单位长度总电容以及主导体和相邻导体之间的单位长度耦和电容。为了验证提出方法的准确性和有效性,进行了一系列验证实验。实验结果表明,提出的互连线二维电容提取技术在寄生电容计算精度上平均提高了140倍,运行时间平均缩了10%。

A Two-Dimensional Capacitance Extraction Technology of Interconnects Based on Segment Reservation Method

With the continuous evolution of manufacturing process and the continuous increase of circuit scale, integrated circuits have gradually entered the post-Moore era. How to accurately and quickly extract parasitic capacitance parameters becomes more and more important to ensure design quality, reduce cost and shorten design cycle. In this paper, a two-dimensional capacitance extraction technology based on the segmented reservation method is proposed. The technique was based on an improved finite difference method, which used non-uniform meshing and solved asymmetric coefficient matrix equations to simulate the cross-section of interconnect structures. The proposed method could efficiently calculate the total capacitance per unit length of the main conductor and the coupling sum capacitance per unit length between the main conductor and adjacent conductors. A series of verification experiments had been completed. The experimental results show that the proposed two-dimensional capacitance extraction technology for interconnects can improve the calculation accuracy of parasitic capacitance by an average of 140 times and shorten the running time by an average of 10 %.