| 基于D触发器锁存抑制进位信号超前的设计 |
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| 引用本文： | 陈永杰.基于D触发器锁存抑制进位信号超前的设计[J].现代建筑电气,2013(11):17-19. |
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| 作者姓名： | 陈永杰 |
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| 作者单位： | 浙江华之建筑设计有限公司,浙江宁波315040 |
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| 摘 要： | 针对时序逻辑电路设计中进位信号同步处理问题,提出了基于D触发器锁存抑制进位信号超前的设计方法,实现了进位信号与输入脉冲同步.通过Proteus软件仿真,验证了设计方法的有效性,将提高电气智能化控制的实时性和安全性.
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| 关 键 词： | 时序逻辑电路 进位信号 D触发器 智能化控制 |
Design of Latched Carry Signal Ahead Based on D Flip-flop |
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| CHEN Yongjie.Design of Latched Carry Signal Ahead Based on D Flip-flop[J].Moder Architecture Electric,2013(11):17-19. |
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| Authors: | CHEN Yongjie |
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| Affiliation: | CHEN Yongjie (Zhejiang Huazhi Architecture Design Co. , Ltd. , Ningbo 315040, China) |
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| Abstract: | For the synchronization of carry signal in temporal logic circuits, the design of latching and inhibiting carry signal ahead based on the D flipk-flop was put forward, which made the synchronization of carry signal and input pulse. This method has been proved by proteus simulation. It will improve the real-time and safety of electrical intelligent control. |
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| Keywords: | temporal logic circuits carry signal D flip-flop intelligent control |
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