A survey on energy-efficient methodologies and architectures of network-on-chip |
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| Affiliation: | 1. Politecnico di Torino, Torino, Italy;2. University of Electronic Science and Technology of China, Chengdu, China;1. Department of Mechanical Engineering, Technical University of Denmark (DTU), Produktionstorvet 425, 2800 Kgs., Lyngby, Denmark;2. STRECON A/S, Stødagervej 5, Sønderborg 6400, Denmark;1. Department of Electronics and Communication Engineering, Malaviya National Institute of Technology, Jaipur, Rajasthan, 302017, India;2. Department of Electronics and Communication Engineering, Swami Keshvanand Institue of Technology Management & Gramothan, Jaipur, Rajasthan, 302017, India;3. Dept. of Electrical Engineering & Dept. of Computer Science & Engineering, Indian Institute of Technology (IIT) Bombay, Mumbai - 400076, India;4. Department of Electronics & Communication Engineering, BML Munjal University (BMU), Gurgaon, Haryana, 122413, India;1. North Dakota State University, USA;2. COMSATS Institute of Information Technology, Abbottabad, Pakistan |
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| Abstract: | Integration of large number of electronic components on a single chip has resulted in complete and complex systems on a single chip. The energy efficiency in the System-on-Chip (SoC) and its communication subset, the Network-on-Chip (NoC), is a key challenge, due to the fact that these systems are typically battery-powered. We present a survey that provides a broad picture of the state-of-the-art energy-efficient NoC architectures and techniques, such as the routing algorithms, buffered and bufferless router architectures, fault tolerance, switching techniques, voltage islands, and voltage-frequency scaling. The objective of the survey is to educate the readers with the latest design-improvements that are carried out in reducing the power consumption in the NoCs. |
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