Decentralized BIST Methodology for System Level Interconnects |
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Authors: | Chauchin Su Shyh-Jye Jou |
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Affiliation: | (1) Department of Electrical Engineering, National Central University, Chung-Li, 32054, Taiwan R.O.C |
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Abstract: | This paper presents an architecture for the local generation of global test vectors for interconnects in a multiple scan chain environment. A unified BIST module is inserted as the gateway for each scan chain to transform the hierarchy of backplane, boards, and scan chains into a one-dimensional array of scan chains. The BIST modules are identical for all the scan chains except for the programmable personalized memories. The personalized memory contains a scan stage type table for the test generation, response compression, and driver contention avoidance. It also contains a scan chain identification number which serves as the seed for the generation of globally distinct serial vectors. The proposed methodology achieves 100% coverage on stuck-at and short faults. |
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Keywords: | interconnect boundary scan BIST DFT |
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