High-Level Cache Modeling for 2-D Discrete Wavelet Transform Implementations |
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Authors: | Y. Andreopoulos P. Schelkens G. Lafruit K. Masselos J. Cornelis |
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Affiliation: | (1) Dept. ETRO, Vrije Universiteit Brussel/IMEC, Pleinlaan 2, B-1050 Brussels, Belgium;(2) Inter-University Micro-Electronics Center—IMEC, Kapeldreef 75, B-3001 Leuven, Belgium;(3) Development Programs Department, Intracom S.A., Athens, Greece |
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Abstract: | The main implementations of the 2-D binary-tree discrete wavelet decomposition are theoretically analyzed and compared with respect to data-cache performance on instruction-set processor-based realizations. These implementations include various image-scanning techniques, from the classical row-column approach to the block-based and line-based methods, which are proposed in the framework of multimedia-coding standards. Analytical parameterized equations for the prediction of data-cache misses under general realistic assumptions are proposed. The accuracy and the consistency of the theory are verified through simulations on test platforms and a comparison is made with the results from a real platform. |
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Keywords: | cache memories discrete wavelet transform implementations theoretical modeling |
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