| 应用于SoC的低功耗MPEG-1／2音频解码IP |
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| 引用本文： | 朱子元.应用于SoC的低功耗MPEG-1／2音频解码IP[J].电子与封装,2008,8(6):30-34. |
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| 作者姓名： | 朱子元 |
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| 作者单位： | 同济大学超大规模集成电路研究所,上海,200092 |
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| 摘 要： | 文章设计了一个低功耗、可复用、MPEG-1／2 LayI／Ⅱ／Ⅲ音频解码IP核。该IP核主要应用于包含一个CPU的嵌入式多媒体处理系统。该IP核包含了一个Software-Core和一个Hardware-Core，在两者的配合下，可以在非常低的时钟频率下高精度解码MPEG-1／2 LayI／Ⅱ／Ⅲ音频码流。在实时解码128kbps／44．1kHz MPEG-1／2LayerⅡ码流时，Hardware-Core工作在5．6448MHz，Software-Core工作在8MHz。文章最后给出另一个该IP在典型SoC系统中的应用。Hardware-Core在CMOS0.18μm工艺下，芯片面积为1520μm×1280μm。
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| 关 键 词： | 片上系统 MPEG 音频解码 IP核 |
A Low Power MPEG-1/2 Audio Decoer IP Core |
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| ZHU Zi-yuan.A Low Power MPEG-1/2 Audio Decoer IP Core[J].Electronics & Packaging,2008,8(6):30-34. |
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| Authors: | ZHU Zi-yuan |
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| Affiliation: | ZHU Zi-yuan ( VLSI Institute Tongji University, Shanghai 200092, China ) |
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| Abstract: | This paper presents a reusable, portable, low cost and low power MPEG-1/2 layer Ⅰ/Ⅱ/Ⅲde- coder IP core. The IP core consists of software core and hardware core. By the corporation between the two parts, they can real-timely decode MPEG-1/2 layer Ⅰ/Ⅱ/Ⅲ audio bit stream at a very low clock frequency. And the IP core is a totally full compliance MPEG audio decoder for providing 6.089 6×10-8 RMS level. In the case decoding a random 128 kbps/44.1 kHz MPEG-1/2 layer Ⅰ/Ⅱ/Ⅲ real-timely, the hardware-core works at 5.644 8 MHz while software-core works at 8MHz. And its die size is 1520μm×1280μm including on-chip SRAM and ROM. |
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| Keywords: | SoC MPEG audio decoder IP core |
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