Dual-regulator dual-decoding-trimmer DRAM voltage limiter forburn-in test |
| |
Authors: | Horiguchi M. Aoki M. Etoh J. Itoh K. Kajigaya K. Nozoe A. Matsumoto T. |
| |
Affiliation: | Hitachi Ltd., Tokyo; |
| |
Abstract: | The authors present a dynamic RAM (DRAM) voltage limiter with a burn-in test mode. It features a dual-regulator dual-trimmer scheme that provides a precise stress voltage in a burn-in test while maintaining a constant limited voltage under normal operation. A regulator is used to preserve a constant difference between the internal burn-in voltage and the supply voltage. Two sets of trimmers reduce the voltage deviations of both the burn-in and normal-operation voltages within ±0.13 V. The circuits are implemented in a 16-Mb CMOS DRAM. A burn-in voltage regulated to ±50 mV at an ambient temperature up to 120°C is obtained simply by elevating the supply voltage to 8 V as in conventional burn-in procedures |
| |
Keywords: | |
|
|