A high-throughput and high-capacity IPv6 routing lookup system |
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Authors: | Yi-Mao Hsiao Yuan-Sun Chu Jeng-Farn Lee Jinn-Shyan Wang |
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Affiliation: | 1. Centre for Innovation in IT Services and Applications (iNEXT), University of Technology, Sydney, Australia;2. ICT Centre, CSIRO, Australia;1. Université de Strasbourg, LSIIT (UMR 7005), CNRS, Illkirch, France;2. Université de Haute Alsace, MIPS (EA 2032), Colmar, France;1. NEC Laboratories Europe, Kurfuersten-Anlage 36, 69115 Heidelberg, Germany;2. Communication Networks Institute, Dortmund University of Technology, Otto-Hahn-Strasse 6, 44227 Dortmund, Germany;1. Department of Telecommunications, Electronic, Electric and Naval Engineering (DITEN), University of Genoa, Via all’Opera Pia 13, 16145, Genoa, Italy;2. National Interuniversity Consortium for Telecommunications (CNIT), Research Unit of the University of Genoa, Via all’Opera Pia 13, 16145, Genoa, Italy |
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Abstract: | With the growing number of routing entries, IP routing lookup has become the major performance bottleneck in backbone routers. In this paper, a complete hardware-based routing lookup system is proposed to achieve high-throughput and high-capacity for IPv6. The proposed system is a cache-centric, hash-based architecture that contains a routing lookup application specific integrated circuit (ASIC) and a memory set. A hash function is used to reduce lookup time for the routing table and ternary content addressable memory (TCAM) effectively resolves the collision problem. The gate count of the ASIC, excluding the binary content addressable memory (BCAM), is about 5306 gates, using an in-house 0.18 μm CMOS single-poly six-metal standard cell library. The results of post-layout simulations show that the ASIC operates in 3.6 ns so that the routing lookup system approaches 260 Mega lookups per second (Mlps), which is sufficient for 100 Gbps networks. The memory density is good, with each routing entry requiring only 64 bits. Moreover, the routing table only needs 10.24 KB on-chip BCAM, 20.04 KB off-chip TCAM and 29.29 MB DRAM for 3.6 M routing entries in the proposed system. |
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