降低系统芯片中跨时钟域设计和验证复杂度的方法

在系统芯片设计中,直接采用现有的跨时钟域信号处理方法不仅设计复杂度高而且验证难度大.为了解决这个问题,将跨时钟域设计与功能设计完全分离,在每个通信接口部件中采用独立的、专用的跨时钟域处理模块统一解决跨时钟域信号的传输问题,并通过封装点对点通信接口和合并处理同一方向的跨时钟域信号,将需要处理的跨时钟域信号的数量减少为方向相反的2组.实验结果表明,该方法能够有效降低跨时钟域设计的验证难度和系统芯片的设计复杂度,并且不会明显增加功能部件的传输延迟和面积开销.

Method for reducing the complexity of clock domain crossing design and its verification in system-on-chips

Existing methods for clock domain crossing (CDC) design were used directly in a system-on-chip (SoC),which result in high design and verification complexity.To solve this problem,a design method was proposed.It separated CDC design completely from functional design and transmits all the CDC signals in an IP design with the help of an independent and dedicated CDC processing module.It also scaled down the total number of CDC signals to two groups of opposite directions through encapsulating point-to-point communication interface as well as processing CDC signals of the same direction in combination.Experiment results demonstrate that this method is able to sharply reduce the verification complexity of CDC design and also simplify the whole SoC design,without significant adding to transfer delay or area cost of an IP design.