基于阵列处理器的最小均方误差检测算法并行设计与实现

针对大规模多输入多输出（MIMO）系统中，最小均方误差（MMSE）检测算法在可重构阵列结构上适应性差、计算复杂度高和运算效率低的问题，基于项目组开发的可重构阵列处理器，提出了一种基于MMSE算法的并行映射方法。首先，利用Gram矩阵计算时较为简单的数据依赖关系，设计时间上和空间上可以高度并行的流水线加速方案；其次，根据MMSE算法中Gram矩阵计算和匹配滤波计算模块相对独立的特点，设计模块化并行映射方案；最后，基于Xilinx Virtex-6开发板对映射方案进行实现并统计其性能。实验结果表明，该方法在MIMO规模为\mathrm{128}\times \mathrm{4}、\mathrm{128}\times \mathrm{8}和\mathrm{128}\times \mathrm{16}的正交相移键控（QPSK）上行链路中，加速比分别2.80、4.04和5.57；在\mathrm{128}\times \mathrm{16}的大规模MIMO系统中，可重构阵列处理器比专用硬件减少了42.6%的资源消耗。

Parallel design and implementation of minimum mean square error detection algorithm based on array processor

In massive Multiple-Input Multiple-Output （MIMO） systems， Minimum Mean Square Error （MMSE） detection algorithm has the problems of poor adaptability， high computational complexity and low efficiency on the reconfigurable array structure. Based on the reconfigurable array processor developed by the project team， a parallel mapping method based on MMSE algorithm was proposed. Firstly， a pipeline acceleration scheme which could be highly parallel in time and space was designed based on the relatively simple data dependency of Gram matrix calculation. Secondly， according to the relatively independent characteristic of Gram matrix calculation and matched filter calculation module in MMSE algorithm， a modular parallel mapping scheme was designed. Finally， the mapping scheme was implemented based on Xilinx Virtex-6 development board， and the statistics of its performance were performed. Experimental results show that， the proposed method achieves the acceleration ratio of 2.80， 4.04 and 5.57 in Quadrature Phase Shift Keying （QPSK） uplink with the MIMO scale of \mathrm{128}\times \mathrm{4}， \mathrm{128}\times \mathrm{8} and \mathrm{128}\times \mathrm{16}， respectively， and the reconfigurable array processor reduces the resource consumption by 42.6% compared with the dedicated hardware in the \mathrm{128}\times \mathrm{16} massive MIMO system.