一种交错并行高速TPC译码器的设计

Turbo乘积码(TPC)作为一种高码率编码在带限通信系统中有着广泛的应用,但是大多数TPC译码器存在结构复杂、资源消耗高、处理时延大的问题.为此,提出了一种交错并行流水线处理结构的译码器,并通过译码过程中测试序列的合理排序以及使用相关运算代替最小欧式距离计算等算法优化设计,简化了译码器的实现复杂度,现场可编程门阵列(FPGA)资源消耗相比传统设计降低了35%,提高了译码速度.在Xilinx公司的FPGA芯片XC5VSX95T上完成了译码器的硬件实现,达到80 Mbit/s的译码速度,通过增加子译码器个数还可进一步提升译码吞吐率.

Design of a high-speed interleaved parallel TPC decoder

Turbo product code (TPC) is applied extensively in bandlimited communication systems as a high-rate code.But most TPC decoders have the problems of complex structure, high resource consumption and large processing latency.For these problems,this paper proposes an interleaved parallel decoder adopting pipelined architecture.By using the reordered test sequences and optimized algorithm such as replacement of the calculation of Euclidean distance by correlation operation, the complexity is reduced, processing latency is shortened and resource consumption is reduced by 35%.Based on the proposed structures, a hardware implementation of TPC decoder on Xilinx XC5VSX95T FPGA is presented.The results show that the proposed decoder architecture can achieve a decoding throughput of 80 Mbit/s, and the decoding throughput can be improved further by increasing the number of sub-decoders.