Energy Efficient Adiabatic Multiplier-Accumulator Design |
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Authors: | Dusan Suvakovic and C Andre T Salama |
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Affiliation: | (1) Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, 10 King's College Road, Toronto, Ontario, M5S 3G4, Canada |
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Abstract: | This paper presents a strategy for minimizing non-adiabatic dissipation in adiabatic arithmetic units. The non-adiabatic dissipation is minimized by architectural design involving a small number of complex logic gates. Circuit design of complex adiabatic gates, based on ordered binary decision diagrams (OBDD), is introduced. An optimized architecture for adiabatic parallel multipliers is proposed and savings in energy dissipation over competing architectures are estimated. Experimental results obtained from implementation of an adiabatic multiply-accumulate (MAC) unit suggest that the proposed strategy provides substantial improvement in energy efficiency over equivalent non-adiabatic and alternative adiabatic implementations, while achieving a competitive operating speed. |
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Keywords: | adiabatic arithmetic circuits multiplier low-power |
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