A Chip-Stacked Memory for On-Chip SRAM-Rich SoCs and Processors |
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Authors: | Saito H. Nakajima M. Okamoto T. Yamada Y. Ohuchi A. Iguchi N. Sakamoto T. Yamaguchi K. Mizuno M. |
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Affiliation: | NEC Corp., Sagamihara, Japan; |
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Abstract: | A dynamic-reconfigurable memory chip is fabricated, by which on-chip memories of an SoC chip can be moved to the memory chip to increase the efficiency of memory usage, and stacked on a logic chip by using three dimensional packaging technology. In the memory chip, many RAM-macros are arrayed and they are connected through two dimensional mesh network interconnects. By using memory-specified network interconnects, area overhead of network interconnects for the memory chip is reduced by 63% and the latency overhead by 43%. Signal lines between the two chips are directly connected by 10-?m-pitch inter-chip electrodes, resulting in fast and low-energy inter-chip transmission. |
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