Below 10 ps/gate operation with buried p-layer SAINT FETs |
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| Authors: | Yamasaki K. Kato N. Hirayama M. |
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| Affiliation: | NTT Atsugi Electrical Communication Laboratory, Atsugi, Japan; |
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| Abstract: | GaAs SAINT FETs with a p-layer buried under the active layer have achieved below 10 ps/gate (9.9 ps/gate) operation for the first time in semiconductor devices. The p-layer formed by Be+ implantation is completely depleted by the built-in potential. It has successfully alleviated the short channel effects without increasing parastic capacitance. |
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