ASIC techniques for high-performance digital signal processing

We describe a high-level ASIC (application specific integrated circuit) synthesis system aimed at rapid and efficient realisation of integer arithmetic “engines” for signal processing bottleneck computations. Novel software features include bit-level scheduling which allocates numerical resources for computation, and a parameter synthesis system which maximises the use of this resource. Underlying synthesis is a generic digit-serial integer arithmetic processing architecture, with module generation capability across a wide parameter space for a useful set of primitive arithmetic operations. We outline the principal components of the tool, and briefly describe some application examples.