Une architecture massivement parallèle intégrée |
| |
Authors: | Bernard Faure S. Mahmoud Karabernou Guy Mazaré Eric Payan Pascal Rubini |
| |
Affiliation: | 1. IMAG/LGI Groupe circuits intégrés, 46, avenue Félix Viallet, F-38031, Grenoble cedex
|
| |
Abstract: | This paper presents a new massively parallel MIMD architecture, halfway between the Connection Machine and hypercubes based on 32-bit processors. It is built from specific 8-bit processors arranged in a 2-D grid and communicating by message transfers. We discuss the communication problems, the instruction set of the basic processing unit, the programmation of the whole array and the use of a high level data-flow language. |
| |
Keywords: | |
本文献已被 SpringerLink 等数据库收录! |
|