HDR视频算法优化及硬件实现

高动态范围(high dynamic range，HDR)视频算法计算复杂度高，硬件实现需要大量逻辑和存储资源，且现有的算法难以满足高分辨率下的实时性要求.针对上述问题，提出一种优化的HDR视频流水线算法，同时利用FPGA的并行可重构特性，完成该算法的硬件实现.算法首先将相机响应函数内置于FPGA的查找表(look-up table, LUT)中，对3帧低动态范围(low dynamic range， LDR)图像进行合并，转换后的数据通过多路并行流水缓存在FPGA的BRAM中; 然后使用快速的全局色调映射算法将结果实时显示输出.最终算法在Xilinx Kintex-7开发板上实验通过，在120 MHz系统时钟频率下，对于1 920×1 080分辨率的视频流，处理速度达到65 f/s，满足了实时性要求.

Optimizing and Implementing the High Dynamic Range Video Algorithom

In contrast to the HDR image processing algorithm, the computation complexity of HDR video processing algorithm make the hardware implementation consume much more logics and storage resources, which poses an enormous obstacle for the existing algorithms to achieve real-time processing. As a consequence, a new algorithm for real-time hardware implementation is demanded. In this paper, we propose a fully pipelined hardware system processing HDR video in real-time, which takes advantage of parallel configurable characteristics of FPGA. Our system obtains a series of low dynamic range (LDR) images adopting varying exposure time algorithm and places their camera response curves in the FPGA look-up table (LUT). Then the translated float data is stored in the BRAM or FIFO modules in parallel pipeline. Finally, the image is displayed in the device by adopting rapid global Tone Mapping algorithm. The entire HDR video processing system is realized in Xilinx Kintex-7 FPGA board. Results show that the processing efficiency can reach 65 f/s for the 1 920×1 080 resolution video when the system clock rate is 120 MHz, which is sufficient for the real-time processing requirements.