Generating synthetic benchmark circuits for accelerated life testing of field programmable gate arrays using genetic algorithm and particle swarm optimization |
| |
| Affiliation: | 1. School of Mathematics, Hefei University of Technology, Hefei, Anhui 230009, China;2. Department of Computer Science, Rice University, Houston, TX 77251, USA;1. College of Foreign Studies, Yanshan University, No. 438 Hebei Street, Qinhuangdao 066004, Hebei, PR China;2. Institute of Electrical Engineering, Yanshan University, No. 438 Hebei Street, Qinhuangdao 066004, Hebei, PR China;3. College of International Programs, Shanghai International Studies University, No. 410 Dong Ti Yu Hui Road, Shanghai 200083, PR China;1. Kalam Institute of Technology, Berhampur, Odisha, India;2. Orissa Engineering College, Bhubaneswar, Odisha, India;3. CV Ramana College of Engineering, Bhubaneswar, Odisha, India;1. College of Management and Economics, Tianjin University, Tianjin 300072, China;2. School of Mathematical Science, Anhui University, Hefei, Anhui 230601, China |
| |
| Abstract: | Accelerated life testing (ALT) of a field programmable gate array (FPGA) requires it to be configured with a circuit that satisfies multiple criteria. Hand-crafting such a circuit is a herculean task as many components of the criteria are orthogonal to each other demanding a complex multivariate optimization. This paper presents an evolutionary algorithm aided by particle swarm optimization methodology to generate synthetic benchmark circuits (SBC) that can be used for ALT of FPGAs. The proposed algorithm was used to generate a SBC for ALT of a commercial FPGA. The generated SBC when compared with a hand-crafted one, demonstrated to be more suitable for ALT, measured in terms of meeting the multiple criteria. The SBC generated by the proposed technique utilizes 8.37% more resources; operates at a maximum frequency which is 40% higher; and has 7.75% higher switching activity than the hand-crafted one reported in the literature. The hand-crafted circuit is very specific to the particular device of that family of FPGAs, whereas the proposed algorithm is device-independent. In addition, it took several man months to hand-craft the SBC, whereas the proposed algorithm took less than half-a-day. |
| |
| Keywords: | Synthetic benchmark circuits (SBC) Accelerated life testing (ALT) Field programmable gate arrays (FPGA) Genetic algorithms (GA) Particle swarm optimization (PSO) |
| 本文献已被 ScienceDirect 等数据库收录！ |
|
