High Efficiency Time Redundant Hardened Latch for Reliable Circuit Design

In a modern high density VLSI design, with higher operating frequency and technology scaling, small critical charge in circuit nodes significantly increases susceptibility to radiation induced transient faults. In this paper, we propose a high efficiency hardened latch using the undesired delay of Schmitt trigger circuit and a special feedback loop to a comparator to build a low overhead time redundancy scheme. The proposed structure masks internal node transient faults also improves the recovery of the output node by transferring the faulty output in two different paths to the comparison circuit’s inputs. Experimental results, simulated in 45 nm CMOS technology, show an acceptable increase in the critical charge compared with the previous hardened latches, with a fair increase in power, delay and area. Monte Carlo simulations have also confirmed the proposed latch resistance to the process, voltage and temperature variations.