一种9.8-mW 1.2-GHz CMOS 低噪声正交输出频率综合器

实现了一种基于标准0.18µm CMOS工艺的应用于北斗导航射频接收机的1.2GHz频率综合器。在频率综合器中采用了一种基于分布式偏置技术实现的低噪声高线性LC压控振荡器和一种基于源极耦合逻辑的高速低开关噪声正交输出二分频器，集成了基于与非触发器结构的高速8/9双模预分频器、无死区效应的延迟可编程的鉴频鉴相器和电流可编程的电荷泵。该频率综合器的输出频率范围从1.05到1.30GHz。当输出频率为1.21GHz 时，在100-kHz和1-MHz的频偏处相位噪声分别为-98.53dBc/Hz和-121.92dBc/Hz。工作电压为1.8V时，不包括输出Buffer的核心电路功耗为9.8mW。北斗射频接收机整体芯片面积为2.41.6 mm2。

A 9.8-mW 1.2-GHz CMOS frequency synthesizer with a low phase-noise LC-VCO and an I/Q frequency divider

A 1.2GHz frequency synthesizer integrated in a RF receiver for Beidou navigation is implemented in standard 0.18µm CMOS technology. A distributed biased varactor LC voltage-controlled oscillator (VCO) is employed to achieve low tuning sensitivity and optimized phase noise performance. A high-speed and low-switching-noise divider-by-2 circuit based on source-coupled logic (SCL) structure is adopted to generate quadrature (I/Q) local oscillating (LO) signal. A high-speed 8/9 dual-modulus prescaler (DMP), a programmable-delay phase frequency detector (PFD) without dead-zone problem, and a programmable-current charge pump (CP) are also integrated in the frequency synthesizer. The frequency synthesizer demonstrates an output frequency from 1.05 to 1.30GHz, and the phase noise is -98.53dBc/Hz at 100-kHz offset and -121.92dBc/Hz at 1-MHz offset from the carrier frequency of 1.21GHz. The power dissipation of core circuits without the output buffer is 9.8mW from a 1.8V power supply. The total area of the receiver is 2.41.6 mm2.