先进CMOS器件中poly-Si/TaN/HfSiON栅结构的干法刻蚀研究

研究了先进CMOS器件中poly-Si/TaN/HfSiON栅结构的干法刻蚀工艺。对于poly-Si/TaN/HfSiON栅结构的刻蚀，我们采用的策略是对栅叠层中的每一层都进行高选择比地、陡直地刻蚀。首先，对于栅结构中poly-Si的刻蚀，开发了一种三步的等离子体刻蚀工艺，不仅得到了陡直的poly-Si刻蚀剖面而且该刻蚀可以可靠地停止在TaN金属栅上。然后，为了得到陡直的TaN刻蚀剖面，研究了多种BCl3基刻蚀气体对TaN金属栅的刻蚀，发现BCl3/Cl2/O2/Ar等离子体是合适的选择。而且，考虑到Cl2对Si衬底几乎没有选择比，采用优化的BCl3/Cl2/O2/Ar等离子体陡直地刻蚀掉TaN金属栅以后，我们采用BCl3/Ar等离子体刻蚀HfSiON高K介质，改善对Si衬底的选择比。最后，采用这些新的刻蚀工艺，成功地实现了poly-Si/TaN/HfSiON栅结构的刻蚀，该刻蚀不仅得到了陡直的刻蚀剖面且对Si衬底几乎没有损失。

Dry etching of poly-Si/TaN/HfSiON gate stack for advanced complementary metal-oxide-semiconductor devices

A novel dry etching process of poly-Si/TaN/HfSiON gate stack for advanced complementary metal-oxide-semiconductor (CMOS) devices is investigated in this paper. Our strategy to process of poly-Si/TaN/HfSiON gate stack is that each layer of gate stack is selectively etched with a vertical profile. Firstly, a three-step plasma etching process is developed to get a vertical poly-Si profile and a reliable etch-stop on TaN metal gate. And then different BCl3-based plasmas are applied to etch TaN metal gate and find that BCl3/Cl2/O2/Ar plasma is a suitable choice to get a vertical TaN profile. Moreover, considering Cl2 almost has no selectivity to Si substrate, BCl3/Ar plasma is applied to etch HfSiON dielectric to improve the selectivity to Si substrate after TaN metal gate is vertically etched off by the optimized BCl3/Cl2/O2/Ar plasma. Finally, we have succeeded in etching of poly-Si/TaN/HfSiON stack with a vertical profile and almost no Si loss utilizing these new etching technologies.