CMOS反相器高功率微波脉宽扰乱效应的建模和分析

本文对受脉宽影响的过剩载流子浓度分布及高功率微波(HPM)扰乱易发性进行解析建模，并利用仿真结果和实验数据对模型进行验证。利用机理分析与模型推导，得到过剩载流子主导闩锁效应中电流放大过程的结论。结果表明，P型衬底中的过剩载流子浓度分布确与HPM脉宽有关，HPM扰乱电压阈值Vp随着脉宽增宽而减小，同时这一变化存在一个拐点，这是由于P型衬底中的过剩载流子累积效应将随着时间推移而受到抑制。文中首次提出HPM脉宽扰乱效应的物理本质是过剩载流子的累积效应。实验验证认为，Vp解析模型能够对CMOS反相器的HPM扰乱易发性进行可靠和准确的预测，并同时考虑工艺、环境温度及版图参数等因素。从模型中可以得到，版图参数LB对脉宽扰乱效应有显著影响：LB较小的CMOS反相器更容易受到HPM的扰乱，这一结论将有助于提出反相器免于HPM扰乱的加固措施。

Modeling and analysis of the HPM pulse-width upset effect on CMOS inverter

We derive analytical models of the excess carrier density distribution and the HPM (high-power microwave) upset susceptibility with dependence of pulse-width, which are validated by the simulated results and experimental data. Mechanism analysis and model derivation verify that the excess carriers dominate the current amplification process of the latch-up. Our results reveal that the excess carrier density distribution in P-substrate behaves as pulse-width dependence. The HPM upset voltage threshold V_p decreases with the incremental pulse-width, while there is an inflection point which is caused because the excess carrier accumulation in the P-substrate will be suppressed over time. For the first time, the physical essence of the HPM pulse-width upset effect is proposed to be the excess carrier accumulation effect. Validation concludes that the V_p model is capable of giving a reliable and accurate prediction to the HPM upset susceptibility of a CMOS inverter, which simultaneously considers technology information, ambient temperature, and layout parameters. From the model, the layout parameter L_B has been demonstrated to have a significant impact on the pulse-width upset effect: a CMOS inverter with minor L_B is more susceptible to HPM, which enables us to put forward hardening measures for inverters that are immune from the HPM upset.