一种基于电阻型数模转换器每级输出3位的6-bit 410-MS/s单通道异步逐次逼近模数转换器

该设计采用SMIC 65-nm CMOS工艺，实现了一款可应用于超宽带通信领域的单通道低功耗6位410-MS/s异步逐次逼近模数转换器(SAR ADC)。通过采用电阻型数模转换器、每级输出3位数字码字结构，以及改进的异步控制逻辑，该ADC在370-MS/s采样率时，无杂散动态范围(SFDR)达到41.95-dB，信号噪声失真比(SNDR)达到28.52-dB。在采样率为410MS/s时，该设计仍能达到40.71-dB的SFDR和30.02-dB的SNDR。通过动态比较器的使用，实现了低功耗设计。测试结果表明，在410-MS/s采样率下，电路总功耗为2.03mW，对应的品质因子(FOM)为189.17fJ/step。

A single channel, 6-bit 410-MS/s 3bits/stage asynchronous SAR ADC based on resistive DAC

This paper presents a single channel, low power 6-bit 410-MS/s asynchronous successive approximation register analog-to-digital converter (SAR ADC) for ultrawide bandwidth (UWB) communication, prototyped in a SMIC 65-nm process. Based on the 3 bits/stage structure, resistive DAC, and the modified asynchronous successive approximation register control logic, the proposed ADC attains a peak spurious-free dynamic range (SFDR) of 41.95 dB, and a signal-to-noise and distortion ratio (SNDR) of 28.52 dB for 370 MS/s. At the sampling rate of 410 MS/s, this design still performs well with a 40.71-dB SFDR and 30.02-dB SNDR. A four-input dynamic comparator is designed so as to decrease the power consumption. The measurement results indicate that this SAR ADC consumes 2.03 mW, corresponding to a figure of merit of 189.17 fJ/step at 410 MS/s.