部分耗尽SOI静态存储器位线电路的研究

对部分耗尽SOI CMOS静态存储器的位线电路进行了模拟和研究,详细分析了BJT效应对SRAM写操作过程的影响,给出了BJT效应在SRAM写操作过程的最坏条件和最好条件下存储单元门管的瞬态泄漏电流的模拟结果;在详细分析BJT效应影响的基础上,对"First Cycle"效应进行了全面的研究.结果表明,"First Cycle"效应对写操作影响较大;研究了位线电容负载对存储单元门管体电位的依赖.最后,给出了研究结果.

A study on Bit-Line Circuit for Partially Depleted SOI CMOS SRAM's

A study on bit-line circuit for CMOS SRAM's based on partially depleted (PD) SOI is presented. BJT effect on the write-cycle of SRAM is discussed, and simulation results of the transient leakage current for worst and best cases are described. Based on the discussion of BJT effect, the "first cycle" effect is investigated, which is shown to have great effect on the write cycle. Results of the study on bit-line capacitors offset are also presented.