System-level performance evaluation of reconfigurable processors |
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| Affiliation: | 1. Electronics Laboratory, Swiss Federal Institute of Technology (ETH), Gloriastrasse 35, ETH Zentrum, CH-8092 Zurich, Switzerland;2. Computer Engineering and Networks Laboratory, Swiss Federal Institute of Technology (ETH) Zurich, ETH Zentrum, CH-8092 Zurich, Switzerland;1. State Key Laboratory of Tribology, Department of Mechanical Engineering, Tsinghua University, Beijing 100084, China;2. School of Mechanical, Electronic and Control Engineering, Beijing Jiaotong University, Beijing 100044, China;3. Jihua Laboratory, Foshan 528000, China;1. Key Laboratory of Artificial Micro- and Nano- Structures of Ministry of Education, School of Physics & Technology, Wuhan University, Wuhan 430072, China;2. Shenzhen Research Institute, Wuhan University, Shenzhen 518000, China;3. First Institute of Oceanography, Ministry of Natural Resources, Qingdao 266061, China;4. Department of Applied Physics, The Hong Kong Polytechnic University, Hong Kong, China;1. A Siemens Business Corporation, Egypt;2. Electronics and Communications Engineering Department, Cairo University, Giza, 12613, Egypt;3. University of Science and technology, Nanotechnology and Nanoelectronics Program, Zewail City of Science and Technology, October Gardens, 6th of October, Giza 12578, Egypt |
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| Abstract: | Reconfigurable architectures that tightly integrate a standard CPU core with a field-programmable hardware structure have recently been receiving increased attention. The design of such a hybrid reconfigurable processor involves a multitude of design decisions regarding the field-programmable structure as well as its system integration with the CPU core. Determining the impact of these design decisions on the overall system performance is a challenging task. In this paper, we first present a framework for the cycle-accurate performance evaluation of hybrid reconfigurable processors on the system level. Then, we discuss a reconfigurable processor for data-streaming applications, which attaches a coarse-grained reconfigurable unit to the coprocessor interface of a standard embedded CPU core. By means of a case study we evaluate the system-level impact of certain design features for the reconfigurable unit, such as multiple contexts, register replication, and hardware context scheduling. The results illustrate that a system-level evaluation framework is of paramount importance for studying the architectural trade-offs and optimizing design parameters for reconfigurable processors. |
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