A pipelined array architecture for Euclidean distance transformation and its FPGA implementation |
| |
| Affiliation: | 1. Department of Nutritional Sciences, The University of Arizona, Tucson, AZ, USA;2. College of Pharmacy and Comprehensive Cancer Center, The Ohio State University, Columbus, OH, USA;3. The University of Arizona Cancer Center, Tucson, AZ, USA;4. Division of Health Promotion Sciences, Mel & Enid Zuckerman College of Public Health, University of Arizona, Tucson, AZ, USA;5. Department of Cellular and Molecular Medicine, College of Medicine, University of Arizona, Tucson, AZ, USA |
| |
| Abstract: | The Euclidean Distance Transform (EDT) is an important tool in image analysis and machine vision. This paper provides an area-efficient hardware solution to the computation of EDT on a binary image. An O(n) hardware algorithm for computing EDT of an n×n image is presented. A pipelined 2D array architecture for harware implementation is designed. The architecture has a regular structure with locally connected identical processing elements. Further, pipelining reduces hardware resources. Such an array architecture is easily scalable to handle images of different sizes and is suitable for implementation on reconfigurable devices like FPGAs. Results of FPGA-based implementation shows that the hardware can process about 6000 images of size 512×512 per second which is much higher than the video rate of 30 frames per second. |
| |
| Keywords: | |
| 本文献已被 ScienceDirect 等数据库收录！ |
|
