Efficient multicast schemes for 3-D Networks-on-Chip |
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| Affiliation: | 1. Intelligent Chips and Systems Research Centre, Guangzhou Institute of Advanced Technology, Chinese Academy of Sciences, Guangzhou, Guangdong, PR China;2. Department of Information Science and Electronic Engineering, Zhejiang University, Hangzhou, Zhejiang, PR China;3. Department of Electrical and Computer Engineering, University of Nevada, Las Vegas, USA;4. University of Enna, Kore, Italy;5. Department of Computer Science and Engineering, The Chinese University of Hong Kong, Hong Kong, PR China;6. Electrical Engineering and Computer Science, University of California, Irvine, USA;1. Departamento Informática e Ingeniería de Sistemas, Universidad de Zaragoza, C/María de Luna, 1, 50018 Zaragoza, Spain;2. I3A Instituto de Investigación en Ingeniería de Aragón (I3A), Edificio I+D+i C/Mariano Esquilor s/n, 50018 Zaragoza, Spain;3. Facultad de Informática, Universidad del País Vasco, Paseo Manuel de Lardizábal, 1, 20018 San Sebastián, Spain;4. HiPEAC NoE (High-Performance Embedded Architectures and Compilers), Spain;1. Global Science Experimental Data Hub Center, Korea Institute of Science and Technology Information, Republic of Korea;2. Department of Computing, Hong Kong Polytechnic University, Hong Kong;3. Department of Electrical and Computer Engineering, University of British Columbia, Canada;1. Guangzhou Institute of Advanced Technology, CAS, China;2. Shenzhen Institute of Advanced Technology, CAS, China;3. The Chinese University of Hong Kong, China;4. University of Nevada, Las Vegas, United States;5. University of Turku, Finland;6. Royal Institute of Technology, Sweden;1. Vienna University of Technology, Department of Computer Engineering, Cyber-Physical Systems, GroupTreitl strasse 3, 3rd floor, 1040 Wien, Austria;2. University of Siegen, Chair for Embedded Systems, Hölderlinstr. 3, 57068 Siegen, Germany |
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| Abstract: | 3-D Networks-on-Chip (NoCs) have been proposed as a potent solution to address both the interconnection and design complexity problems facing future System-on-Chip (SoC) designs. In this paper, two topology-aware multicast routing algorithms, Multicasting XYZ (MXYZ) and Alternative XYZ (AL + XYZ) algorithms in supporting of 3-D NoC are proposed. In essence, MXYZ is a simple dimension order multicast routing algorithm that targets 3-D NoC systems built upon regular topologies. To support multicast routing in irregular regions, AL + XYZ can be applied, where an alternative output channel is sought to forward/replicate the packets whenever the output channel determined by MXYZ is not available. To evaluate the performance of MXYZ and AL + XYZ, extensive experiments have been conducted by comparing MXYZ and AL + XYZ against a path-based multicast routing algorithm and an irregular region oriented multiple unicast routing algorithm, respectively. The experimental results confirm that the proposed MXYZ and AL + XYZ schemes, respectively, have lower latency and power consumption than the other two routing algorithms, meriting the two proposed algorithms to be more suitable for supporting multicasting in 3-D NoC systems. In addition, the hardware implementation cost of AL + XYZ is shown to be quite modest. |
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| Keywords: | Networks-on-Chip (NoCs) Multicast Routing algorithms |
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