A digital TDC with a reduced number of delay line cells |
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| Affiliation: | 1. GANIL/GIP, 26 Bd. Henri Becquerel, 14076 Caen Cedex, France;2. GREYC, ISMRA, 6 Bd. Du Maréchal Juin, 14050 Caen Cedex, France;1. Electronic Technology Area, Instituto Nacional de Técnica Aeroespacial, 28850 Torrejón de Ardoz, Spain;2. Department of Computer Engineering, Space Research Group, Universidad de Alcalá, 28805 Alcalá de Henares, Spain;1. Laboratoire de Génie Electrique, Université de Bejaia, 06000, Algeria;2. IREENA, Saint Nazaire, France;1. Chalmers University of Technology, Department of Physics, Division of Subatomic and Plasma Physics, SE-412 96 Göteborg, Sweden;2. CEA, DEN, DER, Instrumentation, Sensors and Dosimetry Laboratory, Cadarache, F-13108 Saint-Paul-lez-Durance, France;1. Electronics and Information College, Hangzhou Dianzi University, Xiasha Campus, Hangzhou 310018, China;2. State Key Lab of Modern Optical Instrumentation, Zhejiang University, Hangzhou 310027, China |
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| Abstract: | In nuclear physics experiments, a decision maker named as “trigger” gives a bit pattern which allows the fired detectors identification. As the data acquisition dead time is greater than the time between physical events, timing information is essential. We add to the trigger function a Time to Digital Converter (TDC) in order to make a separation between events. The paper describes the architecture chosen for the TDC and illustrates the contribution of each element to the TDC performance. An eight-bit counter is used for the dynamic range of the TDC (in microsecond) associated to a delay line improving the resolution (in nanosecond). The study shows that exploiting the two system clock states (high and low) allows to reduce the number of delay line cells. The Differential Nonlinearity Measurements are given for different resolutions (1, 2 and 5 ns) and illustrate the clock period, the clock duty cycle and the delay line contributions to the TDC performances. |
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