A 19-bit low-power multibit sigma-delta ADC based on data weightedaveraging

This paper describes a low-power multibit sigma-delta analog-to-digital converter (ADC) which achieves 19-b resolution. Multibit quantization and feedback within a sigma-delta loop are shown to provide a power-efficient solution for high-resolution converters. As the linearity of the digital-to-analog converter (DAC) in the feedback path is a critical issue, a comparison of different DAC solutions is made demonstrating the efficiency of the data weighted averaging algorithm. An implementation of this technique within a monolithic sigma-delta ADC is then described. The whole chip, including the digital decimation filter, consumes only 2.7 mW for an 800-Hz output rate. The resolution and linearity improvement brought by data weighted averaging is confirmed by measurements