| 基于DDR2存储器的FIFO设计 |
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| 引用本文： | 占红武,胥芳. 基于DDR2存储器的FIFO设计[J]. 机电工程, 2011, 28(10): 1241-1245 |
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| 作者姓名： | 占红武 胥芳 |
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| 作者单位： | 浙江工业大学机械工程学院,浙江杭州,310014 |
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| 基金项目： | 基金项目：浙江省教育厅科研资助项目（Y201018534）;浙江工业大学特种装备制造与先进加工技术教育部重点实验室开放基金资助项目（2009EF029） |
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| 摘 要： | 针对许多应用系统对FIFO深度不断增长的需求与SRAM技术较低的存储密度之间的矛盾,提出了设计一套使用DDR2存储器,且在FPGA上实现FIFO访问控制的解决方案.设计了一个具有较低访问延迟的DDR2控制器自行实现DDR2存储器所需的自刷新、访存调度、地址译码等操作,通过并发访问和时钟同步,提供了与典型同步FIFO存储...
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| 关 键 词： | 先进先出 DDR2 状态机 现场可编程门阵列 |
Design of FIFO based on DDR2 SDRAM |
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| ZHAN Hong-wu,XV Fang. Design of FIFO based on DDR2 SDRAM[J]. Mechanical & Electrical Engineering Magazine, 2011, 28(10): 1241-1245 |
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| Authors: | ZHAN Hong-wu XV Fang |
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| Affiliation: | ZHAN Hong-wu, XV Fang ( College of Mechanical Engineering, Zhejiang University of Teehnology, Hangzhou 310014, China) |
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| Abstract: | Aiming at the growing demand of FIFO depth and the lower storage density of SRAM technology in many applications, a FIFO access control solution for DDR2 in FPGA was proposed. The scheme was composed by a DDR2 controller with lower access latency, to achieve self-refresh, memory access scheduling, address decoding and other operations, and an access interface compatible with typical synchronous FIFO memories. Some special feature on DDR2 specification was focused on, and a DDR2 controller state machine with low-access latency was given. The FIFO interface was designed to support parallel data reading and writing in a fixed access cycle. The testing results indicate that the FIFO interface has a high access rate, and the depth of the FIFO system can be configured. |
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| Keywords: | first input first output （FIFO） DDR2 state machine field-programmable gate array（FPGA） |
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